Timing Check Errors

Some Times We will Face Such Kind of Errors in our Simulation :

Instead of $setup $hold/$period or other timing related construct in verilog may come.

# ** Error: C:/Xilinx/verilog/src/simprims/X_SFF.v(60): $setup( negedge SRST &&& (srst_clk_enable == 1):527804 ps, posedge CLK:527918 ps, 230 ps );
# Time: 527918 ps Iteration: 0 Instance: /tbTopVerilog_v/uut/\lbc0/addr_2_4_19498\
# ** Error: C:/Xilinx/verilog/src/simprims/X_SFF.v(60): $setup( negedge SRST &&& (srst_clk_enable == 1):527804 ps, posedge CLK:527918 ps, 230 ps );
# Time: 527918 ps Iteration: 0 Instance: /tbTopVerilog_v/uut/\lbc0/addr_2_1_19493\

Reason of Errors : It shows that there must be some timing violation in your simulation .
Easy Removal : If you are working on modelsim then simply give +nospecify option with command Line other tools i.e. VCS / NC-Sim has other options. Please refer the user manual for
that test.

Good Solutions : This is a setup violation message issued by the FF Verilog model, rather than a ModelSim message. It looks like the clk rising edge is too close (< 230 ps) to the falling edge of the reset. If the static timing tools in the Xilinx software does not indicate any problems you may have to look at your test bench in case your timings need reviewing.


These error messages are telling you that you have two rising edges on the clk to this FF that are 1530 ps apart. This violates the FF specification. This looks like it could be either a glitch produced by some clock processing in your design, or the clock generator in your test bench.

To understand these message you need to look in the FF model located at C:/Xilinx/verilog/src/simprims/X_SFF.v. For this particular message; around line 67 you should see some timing definitions and the statement that creates this error message.